The 2006 Symposium on VLSI Circuits, meeting on 15-17 June, 2006 at the Hilton Hawaiian Village in Honolulu, Hawaii and the VLSI Technology Symposium, at the same hotel on 13-15 June, enable technologists and circuit and system designers from around the world to interact and exchange ideas.The close affiliation of these two conferences, a tradition since 1987, gives attendees "a unique opportunity to span the entire VLSI discipline," says Bruce Gieseke, 2006 Symposium Chair. "The Symposium is full of rich and exciting papers."

After two full-day tutorial courses on 14 June, this year's Circuits Symposium program will focus on seven topic areas:

Wireless Communication
Five sessions on RF integrated circuits for wireless communications will include Cellular, WLAN, UWB, Satellite/Mobile Broadcasting and Radar applications. The presentations will cover a broad range of wireless system chip and building block designs, ranging in operation frequency from 400 to 800 MHz in the case of a DVB-H tuner all the way to 182Ghz in the case of a millimeter wave Schottky diode detector.  Circuit design techniques using both low-voltage standard CMOS technologies and high performance SiGe BiCMOS technologies will be discussed.

Opportunities and challenges for RF integrated circuit designs continue to arise as new technologies and wireless standards emerge.  Sharp Corporation will present a direct conversion DVB-H Tuner operating from 400 to 800 MHz, with 184mW power consumption, realized in a 0.5um SiGe BiCMOS technology.  The IC includes a distortion compensated variable-gain low- noise amplifier and an offset cancellation loop for the base-band section.  Several contributions explore the realization of millimeter wave integrated circuits in CMOS technology.  Researchers from the University of Florida will present a 24GHz transmitter with on-chip antenna and a 182GHz Schottky diode detector.  A team from National Taiwan University will discuss a 40GHz voltage-controlled oscillator and a 50GHz distributed amplifier.  The University of California at Los Angeles will contribute a 60GHz CMOS receiver. 

In addition to the emerging applications, advances continue for cellular, WLAN, UWB connectivity and for RF building blocks.  Columbia University will present a 0.5V 900MHz CMOS receiver that demonstrates the critical RF front-end blocks operating from an ultra-low supply voltage.  The University of California at Berkeley will discuss an EDGE RF transmitter using Cartesian feedback implemented in CMOS which overcomes some of the obstacles towards a true single chip phone realization.  Intel Corporation will present a multi-band discrete-time receiver implemented in a 90nm digital CMOS process.  The UWB session includes both MB-OFDM and pulse-based RF transceiver designs.  Finally, recent advances in oscillator and divider designs will also be presented at the symposium.

Data Converters and Analog Techniques
The ever-increasing importance of data converters is reflected by this year's Symposium program, which will start with a data converter short course and a plenary talk on the future roles of data converters, followed by four sessions in the areas of Nyquist ADCs, over-sampled ADCs, and data converter techniques for embedded systems.

A 500MS/s 5b ADC is one of the first ADCs in 65nm to be presented by researchers from MIT, which describes a technique to reduce switching energy for embedded UWB systems. Also the trend continues towards wide bandwidth in over-sampled ADCs. There will be a full session on delta sigma ADCs where Hughes Research Labs will present a 1.4GHz IF band-pass modulator at a 4GHz sample rate.

1V (and below) analog design continues to be an area of active interest and significant advancement in recent years. An example of such work will be presented by Columbia University featuring a 0.5V track-and-hold circuit achieving 60dB SNDR. On the ADC front, researchers from Shizuoka University will present 1V 10-b 100MS/s ADC with only 30mW power. The ADC features a low-power class-AB amplifier to achieve low steady-state current implemented in 90nm CMOS.

Other analog program includes paper sessions on image sensors and real-world interfaces. CMOS image sensors will have a dedicated session this year where Micron will present the world's largest single die CMOS image sensor yielding 4Kx4K pixels of 16 million pixels.

Multi-Gbps Interfaces
The demand for increased bandwidth has resulted in the development of high speed interfaces capable of driving data across long cables and channels as well as short-haul links for memory-CPU communication in computers.  Four technical sessions address issues ranging from clock generation techniques to equalization circuit design approaches and channel effects. 

As the drive to higher data rates continues, equalization techniques are becoming prevalent to combat channel loss and inter-symbol interference at high frequencies.  UCLA and IBM show a low power (5 mW at 6 Gbps) receiver for short-haul applications.  A soft decision feedback equalization technique is used instead of the conventional hard-decision (data slicer based on edge-triggered flip-flop) architecture to relax the critical path, thus saving power.  

Researchers from National Taiwan University present a 38.5GHz clock generator that enables high speed transceiver design.  RMS jitter of 0.24ps at 38GHz is achieved with 52 mW power consumption. 

Performance and power of 1.6 to 9.6 Gbps server, desktop, and mobile I/O lines in a 1.2 V 90nm CMOS process is analyzed in a paper by Intel.  They show that a novel combination of voltage-mode driver (equalized or un-equalized) and RX equalizer delivers the lowest power (12.1mW/Gbps at 7.2Gbps), offering a low power option for short distance links.

Digital Circuit Techniques
As logic technology is moving towards 65 nm and below, on-die variations in the electrical characteristics of transistors and interconnect are presenting difficult challenges to circuit designers.

This year’s contributions in the area of digital circuits focus on
- in-situ die monitoring for process and supply and process variations, and
- power and leakage management techniques applied to a range of entertainment, multimedia and communications processors.  

An in-situ measurement scheme for mapping supply-noise is described which measures 69 mV local supply noise with 5 ns time resolution in a 3G cellular phone processor from Hitachi.

Many papers describe the use of parallel processors for attaining high computational throughput.  The circuits and design methodology of the massively parallel processor from Renesas is based on a matrix architecture, which enhances the performance of multiply-accumulate operations up to 30 GOPS/W. 

A paper from Keio University demonstrates low system power from application specific architecture optimization.  By using a hardware accelerator coupled with a programmable processor core, a real-time face detection core is achieved in 0.79mm² Si using 0.13um CMOS technology.  It can detect 8 faces per frame at 30 fps, while consuming merely 29mW at 1.2 V supply voltage.

SRAM for Ultra-deep submicron technologies
Nine papers on next generation SRAMs from industry and academia will address critical issues related to SRAM cell stability and architectural features at 65 nm and beyond. 

Two key papers are from IBM and Intel.  The IBM paper describes a 32Mb SRAM designed for 65 and 45 nm technologies.  It features read-and-write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms.  Intel’s paper describes a 16-way set associated, single-port 16MB cache for the dual-core Xeon processor using a 0.624 um2 cell in a 65 nm 8-metal layer technology.  Sleep transistors are used in the SRAM array.  Techniques to protect the cache from latent defects and infant mortality failures will be discussed.

Non-Volatile Memory Architecture and Circuits
This year's non-volatile memory session will cover two new flash memory architectures as well as two new emerging technologies, including a 500 MHz SOC MRAM by NEC Corporation and a new CBRAM by Infineon Corporation.  What is a CBRAM? Come to the VLSI Symposium memory session and learn about this new technology, as well other papers.  To further scale the NOR flash array,  Sharp Corporation will discuss its new contact-less virtual ground array architecture with an interesting 32 cell stack string.

Spansion will provide details about their 1.8V 90nm 1Gb OrNAND flash memory solution to the growing removable and embedded data market. This paper discusses their product and memory architecture that was squeezed into 81 mm².  Their paper will also discuss how this 2 bit/cell MirrorBit memory is able to achieve near regular NAND write rates of 3 to 11 MB/S.

Who says non-volatile memories are slow? NEC Corporation will present their MRAM of capable of 500MHz and higher on a 130nm CMOS/240nm MRAM SOC process.  They will introduce two new MRAM cell architectures able to achieved this very high speed performance as well as lower write current.

Evolving DRAM technologies
For SOC (System-On-a-Chip) applications, minimum operational voltage is becoming very critical for DRAM’s.  All four DRAM papers will report new circuit techniques and technologies to meet low operating voltage requirements.

Renesas will report a high performance TwinCell RAM technology in SOI process at 90nm.

Toshiba will report the first ever 6F^{^}2 128 Mb single transistor gain cell-based high density RAM in SOI, which provides a bit yield of 99% and reduced power.

IBM will report a 3T DRAM cell with a gated diode for enhanced speed and data retention time.

Further information can be found on the Symposium web site: www.vlsisymposium.org/index.html.