SIMICS

Silicon Microwave Integrated Circuits and Systems

Publications

Refereed Conference Papers

 

· Changhua Cao, Eunyoung Seok, and Kenneth K. O, “Millimeter-wave CMOS Voltage Controlled-Oscillators,” to appear at Radio and Wireless Symposium, Jan. 2007.

· Changhua Cao, Yanping Ding, and Kenneth K. O, “A 50-GHz Phase-Locked Loop in 130-nm CMOS,” Custom Integrated Circuit Conference (CICC), Sep. 2006

· Changhua Cao, Yanping Ding, Xiuge Yang, Jau-Jr Lin, Ashok Verma, Jenshan Lin, Frank Martin, and Kenneth K. O, “A 24-GHz Transmitter with an On-chip Antenna in 130-nm CMOS,” Symposium on VLSI Circuit, June, 2006, pp. 184-185

· Eunyoung Seok, Changhua Cao, Swaminathan Sankaran, and Kenneth K. O, “A Millimeter-Wave Schottky Diode Detector in 130-nm CMOS Technology,” Symposium on VLSI Circuit, June, 2006, pp. 178-179

· Y. Su, K. K. O, "A 800-uW 26GHz CMOS Tuned Amplifier," RFIC Symposium, pp. 151-154, June. 2006.

· S. Sankaran and K. K. O, “A Schottky Barrier Diode Ultra-Wideband Amplitude Modulation Detector in Foundry CMOS Technology,” June 2006, IEEE Radio Frequency Integrated Circuits Symposium, pp. 309-312.

· J.-J. Lin, H.-T. Wu and K. K. O, “Compact On-Chip Monopole Antennas on 20-W-cm Silicon Substrates for Operation in the 5.8-GHz ISM Band,” IEEE Int. Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 947 – 950, Dec. 2005.

· Changhua Cao, Haifeng Xu, Yu Su, and Kenneth K. O, “An 18-GHz, 10.9-dBm Fully-Integrated Power Amplifier with 23.5% PAE in 130-nm CMOS,” European Solid-State Circuits Conference, Sep.2005, pp.137-140.

· Changhua Cao and Kenneth K. O, “A 90-GHz Voltage-Controlled Oscillator with 2.2-GHz Tuning Range in 130-nm CMOS Process,” Symposium on VLSI Circuits, June 2005, pp.242-243.

· Yanping Ding and Kenneth K. O, "A Low-Power 17-GHz 256/257 Dual-Modulus Prescaler Fabricated in a 130-nm CMOS Process," IEEE RFIC Symp. Dig. Papers, pp. 465-468, June, 2005

· Xiuge Yang, Changhua Cao, Jenshan Lin, Kenneth K. O, and Joe Brewer, "A 2.5GHz Constant Envelope Phase Shift Modulator for Low Power Wireless Applications," RFIC Symposium, June 2005, pp. 663-666.

· Seok and K.K.O, “Rules for Improving Predictability of On-chip Antenna Characteristics in the Presence of Other Metal Structures,” IEEE IITC, 2005

· Yu Su, Jau-Jr Lin, K.K.O, "A 20GHz CMOS RF Down-Converter with an On-chip Antenna," ISSCC Dig. Tech. Papers, pp.270-271, Feb. 2005.

· J.-J. Lin, A. Sugavanam, L. Gao, J. E. Brewer and K. K. O, “On-Wafer Measurement Setups for On-Chip Antennas Fabricated on Silicon Substrates,” IEEE 64th ARFTG Microwave Measurements Conference, pp. 221-225, Dec. 2004.

· J.-J. Lin, X. Guo, R. Li, J. Branch, J. E. Brewer, and K. K. O, “10x Improvement of Power Transmission over Free Space Using Integrated Antennas on Silicon Substrates,” IEEE Custom Integrate Circuits Conf. (CICC) Dig. Tech. Papers, pp. 697-700, 3-6 Oct. 2004.

· J.-J. Lin, X. Guo, R. Li J. E. Brewer and K. K. O, “On-Chip Antenna Gain Measurements in Different Indoor and Outdoor Environments,” IEEE AP-S Intl. Symp. Dig. Tech. Papers, Vol.2, pp. 1611-1614, Monterey, CA, July 2004.

· J. Bohorquez and K. K. O, “A Study of the Effects of Microwave Electromagnetic Radiation on Dynamic Random Access Memory Operation,” IEEE EMC Symposium, Aug. 2004,

· K. K. O, "RF Design Challenges and Opportunities in the International Roadmap for Semiconductors," 2003 Annual Wireless and Microwave Technology Forum, Apr. 2003, Tampa FL.

· X. Guo, R. Li and K. K. O,  "Design Guidelines for Reducing the Impact of Metal Interference Structures on the Performance On-chip Antennas,"  2003  IEEE AP-S Intl. Symp. and USNC/URSI National Radio Science Meeting, Vol. 1, pp 606-609, June, 2003, Columbus, OH.

· R. Li, W. Bomstad, J. Caserta, X. Guo and K. K. O, "Evaluation of Integrated Antennas for Wireless Connection between an Integrated Circuit and an Off-chip Antenna," Proc. of 2003  International Interconnect Conference, pp. 120-122, June 2003, San Francisco, CA.

· K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen, F. Martin, and J. Brewer, "Wireless Communications Using Integrated Antennas," (Invited) Proc. of 2003  International Interconnect Conference, pp 111-113, June, 2003, San Francisco, CA.
Xi Li, J. R. Paviol, B. A. Myers, K. K. O, "A CMOS 802.11b Wireless LAN Transceiver," Proc. of 2003 RFIC Symposium, pp. 41-44, Philladelphia, PA.

· R. Point, Z. Li, W. Foley, B. Ingersoll, J. Borelli, D.  Segarra, D.  Donoghue, C. Liss, M. Mendes, J. Feigin, A. Georgiadis, M. Valery, E. Dawe,  D. Losanno, T. Canchola, R. Quintal, M. Nikitin, B. Jabor, M. Morin,  K. K. O, and G. Dawe, "An RF CMOS Transmitter Integrating a Power Amplifier and a  Transmit/Receive Switch for 802.11b Wireless Local Area Network  Applications," Proc. of 2003 RFIC Symposium, pp. 431-434, Philladelphia, PA.

· W. Bomstad and K. K. O, “Phase and amplitude distribution measurements using a compact test range applicable to wireless clock distribution,” 2002 IEEE AP-S Intl. Symp. and USNC/ URSI National Radio Science Meeting, Vol. 3, pp 726-729, San Antonio, TX. 

· X. Guo, J. Caserta, R. Li, B. Floyd, and K. K. O, “Propagation Layers for Intra-Chip Wire?less Interconnection Compatible with Packaging and Heat Removal,” 2002 Symposium on VLSI Technology, pp. 36-37, June, 2002, Honolulu, HI. 

· D.-J. Yang, and K. K. O, “A Monolithic CMOS 10.4-GHz Phase Locked Loop,” Accepted to 2002 Symposium on VLSI Circuits, June 2002, Honolulu, HI. 

· A. B. M. Harun-ur Rashid, S. Watanabe, T. Kikkawa, X. Guo, and K. K. O, “Interference Suppression of Wireless Interconnection in Si Integrated Antenna,” Accepted to 2002 International Interconnect Conference. 

· T. O. Dickson, B. Floyd, and K. K. O, “Jitter in a Wireless Clock Distribution System,” Accepted to 2002 International Interconnect Technology Conference. 

· T. O. Dickson, D. Bravo, and K. K. O, “Noise Coupling to On-Chip Antennas,” Accepted 2002 IEEE International Symposium on EMC. 

· K. K. O, X. Li, F.-J. Huang, and B. Foley, “CMOS Components for 802.11b Wireless LAN Applications,” (Invited) 2002 RFIC Symposium. 

· K. K. O, N.-K. Park, and D.-J. Yang, “1/f Noise of NMOS and PMOS Transistors and their Implications to Design of Voltage Controlled Oscillators,” (Invited) 2002 RFIC Symposium. 

· F.-J. Huang, and K. K. O, “A 2.4-GHz Single-Pole, Double-Throw T/R Switch with 0.8-dB Insertion Loss Implemented in a CMOS Process,” Accepted to 2001 European Solid State Circuits Conference, Vienna, Austria. 

· K. K. O, J. T. Colvin, T. Chen, C.-M. Hung, K.-H. Kim, B. Floyd, and F.-J. Huang, “Effects of Substrate Resistances for the Noise Performance of RF Circuits Implemented in Silicon-Based Technologies,” (Invited) 16th International Conference on Noise in Physical Systems and 1/f Fluctuations. 

· N.-K. Park, and K. K. O, “Comparison of 1/f Noise of 0.25 um-NMOS and PMOS Transistors from Deep-subthreshold to Strong Inversion.” Accepted to 16th International Conference on Noise in Physical Systems and 1/f Fluctuations.

· K. Kim, W. Bomstad, and K. K. O“A Plane Wave Model Approach to Understanding Propagation in an Intra-chip Communication System,” 2001 IEEE AP-S International Symposium and USNC/URSI National Radio Science Meeting, vol. 2, pp. 166-169, Boston, MA.

· B. Floyd, C.-M. Hung, and K. K. O, “15-GHz Wireless Interconnect Implemented in a 0.18-mm CMOS Technology Using Integrated Transmitters, Receivers, and Antennas,” Digest of Technical Papers, 2001 VLSI Symposium on Circuits, pp.155-158, Kyoto, Japan, 2001.

· S.-M. Yim, and K. K. O, “Demonstration of a Switched Resonator Concept in a Dual-Band Monolithic CMOS LC-Tuned VCO,” Proceedings of 2001 Custom Integrated Circuits Conference, pp 205-208, San Diego, CA, 2000. 

· X. Li, T. Brogan, B. Myers, and K. K. O, “A Comparison of CMOS and SiGe LNA’s and Mixers for Wireless LAN Application,” Proceedings of 2001 Custom Integrated Circuits Con?ference, pp. 531-534, San Diego, CA, 2000. 

· K. Kim. H. Yoon, and K. K. O, “On-Chip Wireless Interconnection with Integrated Antennas,” Technical Digest of IEDM, pp. 485-488, San Francisco, 2000. 

· S.-M. Yim, T. Chen and, K. K. O, “The Effects of a Ground Shield on Spiral Inductors Fab?ricated in a Silicon Bipolar Technology,” 2000 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 157-160, Minneapolis, MN, Sep. 2000. 

· H. Yoon, K. Kim, and K. K. O, “Interference Effects on Integrated Dipole Antennas by a Metal Cover for an Integrated Circuit Package,” 2000 IEEE AP-S International Symposium and USNC/URSI National Radio Science Meeting, pp. 782- 785, Salt Lake City, UT, July 2000. 

· C.-M. Hung, L. Shi, I. Lagnado, and K. K. O, “A 25.9-GHz Voltage-Controlled Oscillator Fabricated in a CMOS Process,” 2000 VLSI Symposium on Circuits, pp. 100 - 101, Honolulu, HI, June 2000. 

· D. Bravo, H. Yoon, K. Kim, B. Floyd, and K. K. O, “Estimation of the Signal-to-Noise Ratio for On-Chip Wireless Clock Signal,” 2000 International Interconnect Technology Conference, pp. 9 - 11, San Francisco, CA, June 2000. 

· B. Floyd, C.-M. Hung, and K. K. O, “The Effects of Substrate Resistivity on RF Component and Circuit Performance,” 2000 International Interconnect Technology Conference, pp. 164 - 166, San Francisco, CA, June 2000 

· F.-J. Huang, and K. K. O, “A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a 0.5-mm CMOS Process,” 2000 Custom Integrated Circuits Conference, pp. 341-344, Orlando, FL, May 2000. 

· C.-M. Hung, B. A. Floyd and K. K. O, “A Fully Integrated 5.35-GHz CMOS VCO and a Prescaler,” Digest of Papers for 2000 IEEE RFIC Symposium, pp. 69-72, Boston, MA, May 2000. 

· B. A. Floyd, K. Kim, K. K. O, “Wireless Interconnection in a CMOS IC with Integrated Antennas,” IEEE International Solid-State Circuits Conference, pp. 328-329, San Francisco, CA, Feb. 2000. 

· C.-M. Hung and K. K. O, “An 1.1-GHz Packaged CMOS VCO with Phase Noise of -126 dBc/Hz at a 600-kHz Offset,” Proc. of 1999 European Solid-State Circuits Conference, pp.330-333, Duisburg, Germany, Sep. 1999. 

· K. Kim and K. K. O, Proc. “Integrated Dipole Antennas on Silicon Substrates for Intra-Chip Communication,” 1999 IEEE AP-S International Symposium and USNC/URSI National Radio Science Meeting, pp.1582-1585, Orlando, FL, July 1999. 

· B. A. Floyd, and K. K. O_, “The Projected Power Consumption of a Wireless Clock Distribution System and Comparison to Conventional Systems,” Proceedings of the 1999 IITC, pp. 248-251, San Francisco, CA, June 1999. 

· B. A. Floyd, J. Mehta, C. Gamero, and K. K. O_, “A 900-MHz 0.8-mm CMOS Low Noise Amplifier with 1.2-dB Noise Figure,” Proceedings of 1999 Custom Integrated Circuits Con?ference, pp. 661-664, San Diego, CA, May 1999. 

· K. K. O, K. Kim, B. A. Floyd, J. Mehta, and H. Yoon, “Inter and Intra-Chip Wireless Clock Signal Distribution Using Microwaves: A Status of an Initial Feasibility Study,” Gov?ernment Microcircuit Applications Conference (Invited), pp. 306-309, Monterey, CA, Mar. 1999. 

· T. Chen, K. Kim and K. K. O, “Application of a New Circuit Design Oriented Q Extraction Technique to Inductors in Silicon IC’s,” Tech. Digest of IEDM98, pp. 527-530, San Francisco, CA, Dec. 1998. 

· Y. Ho and K. K. O, “1.0-V and 1.5-V Operation of 4-GHz Tuned Amplifiers Implemented in a 0.1-mm CMOS Technology on Bulk and SOI Substrates,” IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Paper III.2, Ann Arbor, MI, Sep. 1998 (4 pages). 

· J. T. Colvin, S. Bhatia, and K. K. O, “A Bond-Pad Structure for Reducing Effects of Sub?strate Resistance on LNA Performance in a Silicon Bipolar Technology,” Proceedings of 1998 IEEE BCTM, pp 109-112, Minneapolis, MN., Sep. 1998. 

· K. Kim and K. K. O, “Characteristics of Integrated Dipole Antennas on Bulk, SOI, and SOS Substrates for Wireless Interconnection,” SRC Techcon 98, Paper 8.2, p. 101, Las Vegas, NV, Sep. 1998. 

· B. Floyd and K. K. O, “An Initial Feasibility Study of a Wireless Clock Distribution System for High Performance Microprocessors,” SRC Techcon 98, Paper 8.1, p. 100, Las Vegas, NV, Sep. 1998.

· K. Kim and K. K. O, “Characteristics of Integrated Dipole Antennas on Bulk, SOI, and SOS Substrates for Wireless Communication,” Proceedings of the IITC, pp 21-23, San Francisco, CA, June 1998. 

· K. K. O, Y.-C. Ho, K. Kim, B. Floyd, C.-M. Hung, C. Wann, Y. Taur, I. Lagnado, “Applications of a 0.1-mm CMOS Technology on Bulk, SOS, and SOI Substrates for Tuned Amplifiers,” 1998 digest of papers, Government Microcircuit Applications Conference (Invited), pp. 175 - 178, Arlington, VA, Mar. 1998. 

· K. Kim, Y.-C. Ho, B. Floyd, C. Wann, Y. Taur, I. Lagnado and K. K. O, “4-GHz and 13-GHz Tuned Amplifiers Implemented in a 0.1-mm CMOS Technology on SOI and SOS Sub?strates,” Digest of papers, 1998 International Solid-State Circuits Conference, pp. 134-135, San Francisco, CA, Feb. 1998. 

· M. Rowley, S.-J. Lim, J. G. Harris, and K. K. O, “Implementation of Photo-Imagers in a 0.8-mm Double Polysilicon Bipolar Process,” 1997 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 116-119, Minneapolis, MN, Sep. 1997. 

· C. G. Splain and K. K. O, “Ultra-low Voltage Complementary Metal Oxide Semiconductor (ULV-CMOS) Circuits: Bulk CMOS Operation Below Threshold (V_TO),” Proc. IEEE South?east Conf. ‘96, pp. 670-673, Tampa, FL, Apr. 1996. 

· C. Tsai, B. Scharf, P. Garone, P. Humphries, and K. K. O, “A Double-Spacer Technology for the Formation of Very Narrow Emitter (0.3-mm) Double-Polysilicon Bipolar Transistors using 0.8-mm Photolithography,” 1995 IEEE Bipolar Circuits and Technology Meeting, pp. 97-100, Minneapolis, MN., Oct. 1995. 

· K. K. O, C. Tsai, T. Tewksbury, G. Dawe, C. Kermarrec, and J. Yasaitis. “A double-polysilicon bipolar process with a 0.3-mm minimum emitter width and NMOS transistors for low power wireless applications,” Proc. MTT-S International Microwave Symposium, vol. 2, pp. 531-534, Orlando, FL, May 1995. 

· K. K. O, T. Tewksbury, G. Dawe, C. Tsai, P. Garone, B. Scharf, C. Kermarrec, and J. Yasaitis, “A low cost and low power silicon npn bipolar process with NMOS transistors and its wireless applications,” Proc. 1995 IEEE International Topical Symp. on Technologies for Wireless Appls., pp. 93-98, Vancouver, BC, Canada, Feb. 1995. 

· K. K. O, P. Garone, C. Tsai, B. Scharf, M. Higgins, D. Mai, C. Kermarrec, and J. Yasaitis, “A Double-Polysilicon Self-Aligned npn Bipolar Process (ADRF) with Optional NMOS Transis?tors for RF and Microwave Applications,” Proceedings of the 1994 BCTM, pp. 221~pp. 224, Minneapolis, MN, Oct. 1994. 

· A. N. Karanicolas, K. K. O, J. Y. Wang, H.-S. Lee, and R. Reif, “A High Frequency Fully Differential BiCMOS Operational Amplifier,” Proceedings of the IEEE 1990 CICC, paper 8.3, Boston, MA, May 1990.

· K. K. O, H.-S. Lee, and R. Reif, “2 mm BiCMOS Process with Fully Optimized MOS and Bipolar Transistors,” Proceedings of the First International Symposium on BI/CMOS, pp. 65-72, ECS Proceeding Vol. 89-8, Aug. 1989. 

· K. K. O, H.-S. Lee, R. Reif, W. Frank, W. Metz, and T. Gillis, “A Bipolar Structure with Semi-Dielectric Device Isolation by Selective Epitaxial Growth,” Proceedings of 1988 Bipo?lar Circuits and Technology Meeting, pp. 245-248, Minneapolis, MN, Sep. 1988. 

· T. R. Yew, K. K. O, and R. Reif, “Low Temperature (800 ^oC) Ultra-low-Temperature Chemical Vapor Deposition on Si Wafers with SiO₂ Patterns” Semiconductor Research Corporation TECHCON’88, pp. 170-173, Dallas, TX, Oct. 1988. 

· K. K. O, H.-S. Lee, R. Reif, and W. Frank, “A 2-mm BiCMOS Process Utilizing Selective Epitaxy,” Semiconductor Research Corporation TECHCON’88, pp. 170-173, Dallas, TX, Oct. 1988. 

· K. K. O, H.-S. Lee, and R. Reif, “2 mm BiCMOS Process with Fully Optimized MOS and Bipolar Transistors,” Extended Abstract of 171st ECS Meeting, Vol. 87-1, pp. 407-408, Philadelphia, PA, May, 1987.

 

Refereed Journal Papers

 

· Changhua Cao and Kenneth K. O, “A 140-GHz Fundamental Mode Voltage-Controlled Oscillator in 90-nm CMOS Technology,” Microwave and Wireless Component Letters, Oct. 2006.

· Changhua Cao and Kenneth K. O, “Millimeter-Wave Voltage-Controlled Oscillators in 0.13-μm CMOS Technology,” IEEE Journal of Solid-State Circuits, June, 2006. pp. 1297-1304

· Kwangchun Jung and Kenneth K. O, “A CMOS single-pole-four-throw switch,” IEEE Microwave Wireless Component Letters, vol. 16, no.3, pp. 128-130, Mar. 2006.

· Changhua Cao, Eunyoung Seok and Kenneth, K. O, “192-GHz Push-push VCO in 0.13-μm CMOS,” IEE Electronics Letters, vol. 42, no. 4, Feb. 2006, pp 208-209.

· Changhua Cao and Kenneth K. O, “A Power Efficient 26-GHz 32:1 Static Frequency Divider in 130-nm Bulk CMOS,” IEEE Microwave and Wireless Component Letters, Nov. 2005, pp. 721-723.

· S. Sankaran and K. K. O, “Schottky barrier diodes for millimeter wave detection in a foundry CMOS process,” IEEE Electron Device Letters, vol. 26, no. 7, pp. 492-494, July 2005.

· S. Sankaran and K. K. O, “A Schottky Diode with Cut-off Frequency of 400 GHz Fabricated in 0.18-µm CMOS,” IEE Electronics Letters, vol. 41, no. 8, pp. 506-508, Apr. 2005.

· J.-J. Lin, L. Gao, A. Sugavanam, X. Guo, R. Li, J. E. Brewer and K. K. O, “Integrated Antennas on Silicon Substrates for Communication Over Free Space,” IEEE Electron Device Letters, Vol. 25, NO. 4, pp. 196-198, April 2004.

· D.-J. Yang, and K. K. O, “A 14-GHz 256/257 Dual Modulus Prescaler with Secondary Feedback and its Application to a Monolithic CMOS 10.4-GHz Phase Locked Loop,” IEEE Trans. of MTTS, Vol. 52, no. 2, pp 461-468,  Feb 2004.  

· F.-J. Huang, and K. K. O, " Single-pole Double-Throw CMOS Switches for 900-MHz and 2.4-GHz Applications," Accepted for publication to IEEE J. of Solid-State Circuits, Vol 39, no. 1, pp 35-41, Jan 2004.

· Z.-B. Li, H.-Y. Yoon, and K. K. O, “5.8 GHz CMOS T/R Switches with High and Low Substrate Resistances in a 0.18-mm CMOS Process,” IEEE Microwave and Wireless Components Letters, Volume: 13 Issue: 1 , 2003,  pp 1 -3.

· Z.-B. Li and K. K. O, “A 900 MHz 1.5-V CMOS Voltage Controlled Oscillator using Switched Resonators with a Wide Tuning Range,” Accepted to IEEE Microwave and Wireless Components Letters, Vol. 13, no. 4, pp 137-139, Apr 2003. 

· C.-M. Hung, and K. K. O, “A Fully Integrated 1.5-V 5.5-GHz CMOS Phase Locked Loop,” IEEE J. of Solid State Circuits, Vol. 37, no. 4. Apr 2002. 

· F.-J. Huang, and K. K. O, “A Schottky Diode Clamped Merged Drain CMOS Structure,” Solid State Electronics, 2002. 

· S.-M. Yim and K. K. O, “The Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors,” IEEE J. of Solid-State Circuits, Vol. 37, no. 2, pp 237-244, Feb 2002. 

· B.-A. Floyd, C.-M. Hung, and K. K. O, “A 15-GHz Wireless Interconnect Implemented in a 0.18-mm CMOS Technology Using Integrated Transmitters, Receivers, and Antennas,” IEEE J. of Solid-State Circuits, Vol. 37, no. 5, pp 543-552, May 2002. 

· B.-A. Floyd and K. K. O, “A 23.8-GHz SOI CMOS Tuned Amplifier,” IEEE Trans. on Microwave Theory and Techniques, Vol. 50, no. 9, Sept. 2002. 

· J. Mehta, and K. K. O, “Switching Noise of Integrated Circuits (ICs) Picked up by a Planar Dipole Antenna Mounted Near the ICs,”  IEEE Trans. on Electro-Magnetic Compatibility, Vol 44, no. 2, pp. 282-290, May 2002. 

· B. Floyd and K. K. O, “SOI and bulk CMOS frequency dividers operating above 15 GHz,” IEE Electronics Letters, vol 37, issue 10, pp. 617-618, May, 2001. 

· N. Park and K. K. O, “Body Bias Dependence of 1/f Noise in NMOS Transistors from Deep-Subthreshold to Strong Inversion,” IEEE Trans. on Electron Devices, vol. 48, no. 5, pp. 999-1001, 2001. 

· F.-J. Huang, and K. K. O, “A 900-MHz T/R Switch with a 0.8-dB Insertion Loss Implemented in a 0.5-mm CMOS Process,” IEEE J. of Solid State Circuits, vol. 36, no. 3, pp 486-492, March 2001. 

· C. M. Hung, B. Floyd, and K. K. O, “A Fully Integrated 5.35-GHz CMOS VCO and a Prescaler,” IEEE Trans. on Microwave Theory and Techniques, vol. 49. no. 1, 17-22, Jan. 2001. 

· C.-M. Hung and K. K. O, “An 1.1-GHz Packaged CMOS VCO with Phase Noise of -126 dBc/Hz at a 600-kHz Offset,” IEEE J. of Solid-State Circuits, vol. 35, no. 1, pp. 100 - 103, Jan. 2000. 

· H. Yan, M. Biyani, and K. K. O, “A High-Speed CMOS Dual-Phase Dynamic-Pseudo NMOS ((DP)2) Latch and Its Application in Dual-Modulus Prescaler,” IEEE J. of Solid State Circuits, vol. 34, no. 10, pp. 1400 - 1404, October, 1999. 

· J. Colvin, S. Bhatia, and K. K. O, “Effects of Substrate Resistances on LNA Performance and a Bond-Pad Structure for Reducing the Effects in a Silicon Bipolar Technology,” IEEE J. of Solid State Circuits, vol. 34, no. 9, pp. 1339 - 1344, Sep. 1999. 

· C.-M. Hung and K. K. O, “An 1.24-GHz Monolithic CMOS VCO with Phase Noise of -137 dBc/Hz at a 3-MHz Offset,” IEEE Microwave and Guided Wave Letts., vol. 9, no. 3, pp. 111-113, March, 1999.

· Y.-C. Ho, K. Kim, B. Floyd, C. Wann, Y. Taur, I. Lagnado and K. K. O, “4-GHz and 13-GHz Tuned Amplifiers Implemented in a 0.1-mm CMOS Technology on SOI and SOS Substrates,” IEEE J. of Solid-State Circuits, vol. 33, no. 12, pp 2066-2073, December, 1998. 

· F.-J. Huang and K. K. O, “Schottky Clamped NMOS Transistors Implemented in a Conven?tional 0.8-mm CMOS Process,” IEEE Elec. Dev. Letts, vol. 19, no. 9, pp 326-328, September, 1998. 

· K. K. O, “Estimation of Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies,” IEEE J. of Solid-State Circuits, vol. 33, no. 8, pp 1249-1252, August, 1998. 

· M.-Y. Chuang, M. Law, and K.K. O, “Three-dimensional Base Distributed Effects of Long Stripe BJT’s: AC Effects on Input Characteristics,” IEEE Transaction on Electron Devices, vol. 45, no. 9, pp. 1993-2001, September, 1998. 

· K. K. O and B. Scharf, “Effects of Buried Layer Geometry on Characteristics of Double Polysilicon Bipolar Transistors,” IEEE Electron Device Letters, vol. 19, no. 5 pp 160 - 162, May, 1998. 

· C.-M. Hung, I-C. Wu, Y.-C. Ho, and K. K. O, “High Q Capacitors (> 150 @ 900 MHz) Implemented in a CMOS Process for Wireless Applications,” IEEE Transaction on MTT, vol. 46, no. 5, pp 505 - 511, May, 1998. 

· C. Smithhisler, K. Kim, J. Colvin, Y.-C. Ho, and K. K. O, “Design Considerations for Integrated Inductors in Conventional CMOS Technologies,” Solid-State Electronics, vol. 42, no. 5 pp. 699-704, May 1998. 

· M.-Y. Chuang, M. Law, and K. K. O, “Three-dimensional base distributed effects of long stripe BJT’s: base resistance at DC,” IEEE Trans. on Electron Devices, vol. 45, no. 2, pp. 439 - 446, February, 1998. 

· F.-J. Huang and K. K. O, “Metal-Oxide Semiconductor Field Effect Transistors Using Schottky Barrier Drains (SBDR),” IEE Electronics Letters, vol. 33, no. 15, pp. 1341-1342, July, 1997. 

· K. Kim and K. K. O, “Characteristics of an Integrated Spiral Inductor with an Underlying n-well,” IEEE Trans. Electron Devices, vol. 44, pp. 1565 - 1567, September 1997. 

· Y.-C. Ho, M. Biyani, J. Colvin, C. Smithhisler, and K. K. O, “A 3-V Low Noise Amplifier Implemented Using a 0.8-mm CMOS Process with Three Metal Layers for 900 MHz Opera?tion,” IEE Electronics Letters, vol. 32, no. 13, pp. 1191-1193, June 1996. 

· K. K. O, P. Garone, C. Tsai, G. Dawe, B. Scharf, T. Tewksbury, C. Kermarrec, and J. Yasaitis, “A Low Cost and Low Power Silicon npn Bipolar Process with NMOS Transistors (ADRF) for RF and Microwave Applications,” IEEE Trans. Electron Devices, vol. 42, no. 10, pp. 1831 - 1840, October, 1995. 

· K. K. O and J. Yasaitis, “Integration of two different gate oxide thickness in a 0.6-mm dual voltage mixed signal CMOS process,” IEEE Trans. on Electron Devices, 42, pp. 190-192, 1995. 

· K. K. O, J. Lutsky, R. Reif, H.-S. Lee, “An NMOS Input Merged Bipolar/Side-wall MOS Transistor with a Bypass Side-wall MOS Transistor (NBIBMOS Transistor),” IEEE Electron Dev. Letts, Vol. 13, No. 11, pp. 563-565, 1992. 

· K. K. O, R. Reif, and H.-S. Lee, “PMOS Input Merged Bipolar/ Side-wall MOS Transistors (PBiMOS Transistors),” IEEE Electron Dev. Letts, Vol. 12, No. 2, pp. 68-70, 1991. 

· A. N. Karanicolas, K. K. O, J. Y. Wang, H.-S. Lee, and R. Reif, “A High Frequency Fully Differential BiCMOS Operational Amplifier,” IEEE Journal of Solid-State Circuits, vol. 26, no. 3, pp. 203-208, 1991. 

· K. K. O, H.-S. Lee, and R. Reif, “BiMOS Transistors: “Merged Bipolar/ Side-wall MOS Transistors,” 47th Annual Device Research Conf., IEEE Trans. Electron Devices, vol. 36, no. 11, p. 2606, November, 1989. 

· K. K. O, R. Reif, and H.-S. Lee, “BiMOS Transistors: “Merged Bipolar/Side-wall MOS Transistors,” Elec. Dev. Lett., vol. EDL 10, pp. 517-519, 1989. 

· K. K. O, H.-S. Lee, and R. Reif, W. Frank, W. Metz, and T. Gillis, “A Shallow Buried Layer Formation Technique Utilizing Diffusion from Implanted Polysilicon Layer,” Elec. Dev. Lett., vol. EDL 10, pp. 319-321, 1989. 

· K. K. O, H.-S. Lee, and R. Reif, “A BiCMOS Process Utilizing Selective Epitaxy for Analog/Digital Applications,” IEEE Trans. Elec. Dev., vol. ED-36, pp. 1362-1368, 1989. 

· K. K. O, H.-S. Lee, R. Reif, and W. Frank, “A 2-mm BiCMOS Process Utilizing Selective Epitaxy,” 46th Annual Device Research Conf., IEEE Trans. Electron Devices, vol. 35, no. 12, p. 2436, December, 1988. 

· K. K. O, H.-S. Lee, R. Reif, and W. Frank, “A 2-mm BiCMOS Process Utilizing Selective Epitaxy,” IEEE Electron Device Lett., Vol. EDL-9, no. 11, pp. 567-569, 1988. 

· T.-R. Yew, K. K. O, and R. Reif, “Silicon epitaxial growth on (100) patterned oxide wafers at 800^oC by ultra low-pressure chemical vapor deposition,” Appl. Phys. Lett., Vol. 52, no. 21, pp. 1797-1799, 1988. 

· K. K. O, and P. E. Cottrell, “Surface Mobility of Holes and Electrons in Silicon as Low temperatures,” 42nd Device Research Conf., IEEE Trans. Electron Devices, vol. 31, no. 12, p. 1976, December, 1984. 

 

Patents

 

· K. K. O and D. –J. Yang, “High Speed Phase Locked Loop,” US Patent # 6,940,322, 2005.

· K. K. O and F. J. Huang, “Semiconductor Diode Clamped Complementary Field Effect Tran?sistor Integrated Circuits,” In preparation for application.

· C. Tsai, K. K. O, and B. Scharf, “Double-Spacer Technique for Forming a Bipolar Transistor with a Very Narrow Emitter,” US Patent # 5,866,462, Issued, February 2, 1999.

· K. K. O, “Process for Integration of Gate Dielectric Layers Having Different Parameters in an IGFET Integrated Circuit,” United States Patent # 5,432,114, Issued on July 11th, 1995.

· K. K. O, H.-S. Lee, and R. Reif, “Merged Bipolar and Insulated Gate Transistors,” United States Patent # 5,028,977, Issued on July 2, 1991.

· K. K. O, L. G. Pearce, and D. A. Matlock, “CMOS Device Having Reduced Spacing Between N and P Channel Transistor Pair,” United States Patent # 4,829,359, Issued on May 9th, 1989.

 

Invited Talks

 

· K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen and J. Brewer, “Antennas in Silicon Integrated Circuits,” (Invited) Motorola Antenna Workshop, June 2003.

· K. K. O, K. Kim, B. Floyd, J. Mehta, H. Yoon, C.-M. Hung, D. Bravo, T. Dickson, X. Guo, R. Li, N. Trichy, J. Caserta, W. Bomstad, J. Branch, D.-J. Yang, J. Bohorquez, L. Gao, A. Sugavanam, J.-J. Lin, J. Chen and J. Brewer, “Integrated antennas on silicon substrates and their applications,”  (Invited) 2003  International Microwave Symposium Workshop, June 2003, Philadelphia, PA.

· B. Floyd, X. Guo, J. Caserta, W. Bomstad, T. Dickson, J. Mehta, C.-M. Hung, and K. O, “Wireless Clock Distribution,” (Invited), ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Dec. 2002, Monterey CA 

· K. K. O, J. T. Colvin, T. Chen, C.-M. Hung, K.-H. Kim, B. Floyd, and F.-J. Huang, “Effects of Substrate Resistances for the Noise Performance of RF Circuits Implemented in Silicon-Based Technologies,” (Invited) 16th International Conference on Noise in Physical Systems and 1/f Fluctuations. 

· K. K. O, K. Kim, B. Floyd, J. Mehta, and H. Yoon “A Feasibility Study for Inter and Intra-Chip Wireless Clock Signal Distribution Using Microwaves,” IMAPS Advanced Technology Workshop on Next Generation IC and Package Design, July 1998, Hilton Head, South Caro?lina.(Invited)

· K. K. O, K. Kim, B. Floyd, and J. Mehta, “Inter and Intra-Chip Clock Signal Distribution Using Microwaves,” 1997 IEEE Solid State Circuits and Technology Committee Workshop on Clock Distribution, Oct. 1997, Atlanta, GA. (Invited)

· K. K. O, R. Reif, H.-S. Lee, and W. Frank, “A 2-µm BiCMOS Process Utilizing Selective Epitaxy,” 1989 IEEE Solid State Circuits and Technology Committee Workshop on BiCMOS Circuits and Technology, Feb. 1989, New York, NY. (Invited)

· K. K. O, R. Reif, and H.-S. Lee, “MIT Analog BiCMOS Process,” Paper II.3.4, SRC Topical Research Conference on Submicron BiCMOS Technology for the 90s, Cambridge, MA, Dec., 1987. (Invited)
 

Invited Panels

 

· “Enabling Technologies for Next Generation WLAN, WPAN, WHAN: What will win?” The Third IEEE Workshop on Wireless Local Area Networks, Newton, MA, Sep., 2001.
  

Invited Tutorials

· K. K. O, "Design and Analyses of Tuned RF Circuits including the Effects of Process and Component Variations," 2003 Asia-Pacific Microwave Conference, Nov. 2003.

Supervised Theses

 

Ph. D 

· R. Li, A Wireless Clock Distribution System using External Antenna, 2005

· X. Guo, CMOS Intrachip Wireless Clock Distribution, 2005

· S. –M. Yim, 2004

· D. –J. Yang, 2004

· Z. -B. Li, Radio Frequency Circuits for Tunable Multi-band CMOS Receivers for Wireless LAN  Applications, 2004

· Xi Li, Evaluation of Radio Frequency CMOS Integrated Circuit Technology for Wireless Local Area Network Applications, May 2003

· N.-K. Park, 1/f Noise of MOS Field Effect Transistors for Analog Circuit Applications, Aug. 2001. 

· B. Floyd, A CMOS Wireless Interconnect System for Multi-Giga-Hertz Clock Distribution, Apr. 2001. 

· Feng-Jung Huang, Schottky Clamped MOS Transistors for Wireless CMOS Radio Frequency Switch Applications, Apr. 2001. 

· Y.-C. Ho, Implementation and Improvement for RF Low Noise Amplifiers in Conventional CMOS Technologies, Dec. 2000. 

· K.-H. Kim, Design and Characterization of RF components for Inter- and Intra-chip Wireless Communication, Dec. 2000. 

· C.-M. Hung, Investigation of a Multi-GHz Single-Chip CMOS PLL Frequency Synthesizer for Wireless Applications, May 2000. 

 

Master of Science

· Wayne Bomstad, An Ultra-Compact Antenna Test System and Its Analysis in the Context of Wireless Clock Distribution, Aug. 2002. 

· Timothy O. Dickson, Background Noise in CMOS Integrated Circuits and Its Impact on the Performance of a Wireless Interconnect System, May 2002. 

· Narasimhan Trichy Rajagopal, Design of a 4kb DRAM to investigate impact of on-chip wireless interconnects on DRAMS, Dec. 2001. 

· Daniel Bravo, Investigation of Background Noise in Integrated Circuits Relating to the Design of an On-Chip Wireless Interconnect System, Dec. 2000. 

· Saket Bhatia, Analysis and Optimization of a Low-Power Packaged Silicon Bipolar Low Noise Amplifier (LNA) Operating between 4 and 6 GHz, Aug. 1999. 

· Tong Chen, Integrated Inductors in Silicon Integrated Circuits, Dec. 1998. 

· John T. Colvin, Package Interconnect and Substrate Effects on Silicon Bipolar LNA’s Operating in the 2 TO 6 GHz Frequency Range, Dec. 1998. 

· Carlos Gamero, Design Optimization of a Single Stage MOS LNA Using a g_m/ID Based Me